1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory and a fabrication method for the same. More specifically, it relates to a nonvolatile semiconductor memory including a word line electrode interconnect layer pattern for a memory cell array and a fabrication method for the same.
2. Description of the Related Art
An electrically data-erasable programmable read-only memory (EEPROM) is well-known as a nonvolatile semiconductor memory. The EEPROM, in particular, a NAND EEPROM includes a memory cell array comprising memory cells disposed on respective intersections of horizontal word lines and vertical bit lines. Typically, a memory cell is configured by, for example, a MOS transistor having a stacked gate structure of a floating gate and a control gate.
A NAND flash memory structure is provided by connecting multiple memory cell transistors in series, thereby creating a NAND string, and disposing select transistors on both sides of the NAND string. In addition, a memory cell array is configured by arranging element isolating regions in parallel with a memory cell element active area.
In order to ensure that a NAND flash memory cell array provides a lithographic margin for regions that are hard to provide periodicity of a word line end pattern, the line width in those regions is extended to be longer than line widths in the other regions, and thereby making the width of the spacing less than the minimum rule. However, recently, since the original minimum line width is narrow, use of such smaller pattern than the minimum line width is impossible. As a result, inter-interconnect short-circuits may easily occur.
A semiconductor device including a fine line and space pattern with narrower inter-line spacing than the line width has been disclosed. The device has wider adjacent inter-line spacing at the line end pattern than at the central pattern, thereby preventing inter-line short-circuits from occurring in the vicinity of line ends due to an optical intensity distribution produced by lithography process (See Japanese Patent Application Laid-Open No. Hei 7-183301).